The present invention relates in general to electronic circuits, in particular analog voltage comparators, and is especially directed to a new and improved analog comparator architecture having improved immunity to single event effects (upsets, transients) and variations in input offset voltage.
Semiconductor circuits employed in environments prone to incidence of cosmic rays and high energy particles can be disturbed or interrupted by charge deposit anomalies associated with such incidence, to result in what are commonly termed single event effects (SEEs). These effects can include Single Event Transients (SET), where electrical signals are upset from their normal levels, but return to the proper value over time, or single event upsets (SEUs), where the perturbation flips or inverts the state of a storage element, thus creating an incorrect an incorrect logic state that does not return to its correct value over time.
Typical, but non-limiting examples of environments that are subject to such events or upsets include spaceborne systems, as well as airborne and terrestrial systems that operate in the vicinity of the earth""s magnetic poles. Moreover, as improvements in semiconductor manufacturing techniques continue to reduce feature size (and thus increase integration density), there is an escalating probability of event upsets and effects in such systems.
Up to the present, major industry focus has been in the digital arena, particularly digital signal processing applications, where a single bit error caused by an SEU or SEE may cause substantial corruption of the operation of an entire digital system. Efforts to combat the problem in digital applications have included installation of redundant or parallel digital subsystems (including separately clocked or sampling schemes), coupled with majority voting techniques to xe2x80x98maskxe2x80x99 out effects of such event upsets. In contrast, their potential impact on the operation of analog systems has not been substantially pursued, principally due to the fact that the generally linear behavior and recovery properties of analog devices provide a measure of inherent immunity against such events.
However, as increasing numbers of electronic systems, such as high data rate telecommunication systems, are implemented as an integration of both high density analog and digital components in a common support and signal feed and distribution architecture, event upset-sourced anomalies in analog components may propagate and thereby corrupt downstream digital components.
In addition to their susceptibility to single event effects and upsets, analog circuits that employ a built-in reference parameter, such as comparator matched bias current, are prone to exhibit respectively different operational behaviors associated with differences in manufacturing parameters, device mismatches, thermal gradients, and the like. For example, for a given identical comparator design, it can be expected that even the slightest variations in processing conditions of an integrated circuit fabrication methodology will produce comparator circuits having slightly different input offset voltages.
In accordance with the present invention, the above described single event and differential input offset voltage mismatch problem that can occur in analog comparator circuits is effectively obviated by a new and improved comparator architecture that replaces a conventional single analog comparator-based design with an odd plurality of (e.g., three) comparators, whose outputs drive a xe2x80x9cmajority votexe2x80x9d logic block. Each comparator is coupled to receive a respective bias current from an associated bias current source, and has a pair of complementary polarity +/xe2x88x92 inputs coupled to respective (+) and (xe2x88x92) voltage input ports.
Each comparator of the triple comparator input stage is operative to drive the state of its output to one of two logical states (xe2x80x980xe2x80x99/xe2x80x981xe2x80x99) depending upon whether its differential input voltage is greater than the comparator""s internal offset voltage. As each comparator can be expected to have a slightly different input offset voltage due to device mismatches, thermal gradients, and the like, the effective input offset voltage of the multi-comparator input stage is the value of the middle one of the three individual comparators"" offset voltages.
A single event upset (e.g. heavy ion strike) on any comparator within the input stage can cause its output to momentarily transition to the incorrect state. However, the output of the majority voting logic block will remain in the correct state, as only one comparator is upset, a xe2x80x9cmajority votexe2x80x9d on the outputs of the other two comparators producing the correct logic state. Also, a heavy ion strike on any of the bias current sources can cause a momentary loss of bias current. However, this would upset only one of the odd multiple number of comparators in the multi-comparator input stage, so that the output of the majority vote logic block will remain correct.